Digital Design and Computer ArchitectureMorgan Kaufmann, 26 thg 7, 2010 - 592 trang Digital Design and Computer Architecture is designed for courses that combine digital logic design with computer organization/architecture or that teach these subjects as a two-course sequence. Digital Design and Computer Architecture begins with a modern approach by rigorously covering the fundamentals of digital logic design and then introducing Hardware Description Languages (HDLs). Featuring examples of the two most widely-used HDLs, VHDL and Verilog, the first half of the text prepares the reader for what follows in the second: the design of a MIPS Processor. By the end of Digital Design and Computer Architecture, readers will be able to build their own microprocessor and will have a top-to-bottom understanding of how it works--even if they have no formal background in design or architecture beyond an introductory class. David Harris and Sarah Harris combine an engaging and humorous writing style with an updated and hands-on approach to digital design.
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Nội dung
| 3 | |
| 51 | |
Chapter 3 Sequential Logic Design | 103 |
Chapter 4 Hardware Description Languages | 167 |
Chapter 5 Digital Building Blocks | 233 |
Chapter 6 Architecture | 289 |
Chapter 7 Microarchitecture | 363 |
Chapter 8 Memory Systems | 463 |
Appendix A Digital System Implementation | 515 |
Appendix B MIPS Instructions | 551 |
| 555 | |
| 557 | |
Ấn bản in khác - Xem tất cả
Digital Design and Computer Architecture David Money Harris,Sarah L. Harris Không có bản xem trước - 2007 |
Digital Design and Computer Architecture: Arm Edition David Harris,Sarah Harris Không có bản xem trước - 2015 |
Thuật ngữ và cụm từ thông dụng
adder addi alucontrol ALUOp ALUSrcA architecture array assembly language assign Ben Bitdiddle binary numbers block Boolean equation branch bytes cache called chip CLK CLK clock Code Example combinational logic cycle datapath decoder delay downto encoding endmodule execution Exercise flip-flop floating-point FPGA function hardware HDL Example hexadecimal IEEE.STD_LOGIC_1164.all implement input inverter jump latch library IEEE load logic gates loop machine main memory MemtoReg MemWrite microarchitectures microprocessor minterm MIPS architecture MIPS assembly code MIPS processor miss rate module multicycle multiplexer mux2 nextstate operands operation output page table PCSrc pipeline pMOS transistors port propagation R-type register file RegWrite reset rising edge schematic Section sequential circuits shown in Figure shows signal SignImm single-cycle stack STD_LOGIC stored synchronous transistors truth table two’s complement variables Verilog VHDL virtual memory virtual page voltage write